ARM Advanced Microcontroller Bus Architecture by J D Barrow
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Overview: 1.1 Overview of the AMBA specification
The Advanced Microcontroller Bus Architecture (AMBA) specification defines an onchip
communications standard for designing high-performance embedded
microcontrollers.
Three distinct buses are defined within the AMBA specification:
• the Advanced High-performance Bus (AHB)
• the Advanced System Bus (ASB)
• the Advanced Peripheral Bus (APB).
A test methodology is included with the AMBA specification which provides an
infrastructure for modular macrocell test and diagnostic access.
1.1.1 Advanced High-performance Bus (AHB)
The AMBA AHB is for high-performance, high clock frequency system modules.
The AHB acts as the high-performance system backbone bus. AHB supports the
efficient connection of processors, on-chip memories and off-chip external memory
interfaces with low-power peripheral macrocell functions. AHB is also specified to
ensure ease of use in an efficient design flow using synthesis and automated test
techniques.
1.1.2 Advanced System Bus (ASB)
The AMBA ASB is for high-performance system modules.
AMBA ASB is an alternative system bus suitable for use where the high-performance
features of AHB are not required. ASB also supports the efficient connection of
processors, on-chip memories and off-chip external memory interfaces with low-power
peripheral macrocell functions
.
1.1.3 Advanced Peripheral Bus (APB)
The AMBA APB is for low-power peripherals.
AMBA APB is optimized for minimal power consumption and reduced interface
complexity to support peripheral functions. APB can be used in conjunction with either
version of the system bus.
1.2 Objectives of the AMBA specification
The AMBA specification has been derived to satisfy four key requirements:
• to facilitate the right-first-time development of embedded microcontroller
products with one or more CPUs or signal processors
• to be technology-independent and ensure that highly reusable peripheral and
system macrocells can be migrated across a diverse range of IC processes and be
appropriate for full-custom, standard cell and gate array technologies
• to encourage modular system design to improve processor independence,
providing a development road-map for advanced cached CPU cores and the
development of peripheral libraries
• to minimize the silicon infrastructure required to support efficient on-chip and
off-chip communication for both operation and manufacturing test.
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